This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform [1]. The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider. The technology is 0.18um XFAB (EFXH018C)

This paper is submitted by Alberto Gomez Saiz, who is a Mixed Signal IC Design Engineer with over 5 years of experience in industry. He has been involved the design of SoCs for IoT and connectivity, designing state of the art low power analog IP. Alberto holds a MSc. degree in IC design from Imperial College in London, U.K.

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