Here's VSD Talk on "Survey of E31 RISC-V Core Floor Plan and Its Impact on Power, Performance and Area PPA" @RISC-V workshop at IIT
Madras...
Addressing a crowd of close to ~200 RISC-V enthusiasts’ people.
It was really a
pleasure talking about the latest developments in the world of open-source EDA and techniques we used to blend it with E31 RISC-V Core (from SiFive).
It’s a long 40-min technical video, and worth watching.....Take a look...Also, I will keep you all posted on my
next venue, very soon....Hope we meet at your city...So stay tuned
