Another chance, another medium, another platform for us to catch-up personally…. (You might want to forward this email to your colleagues staying close-by any one of below cities, and encourage them to attend this free event to learn more about RISC-V ecosystem in India)

I would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.

I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”

Because India has adopted RISC-V as the national ISA, the time is now to learn from the academic luminaries who created this open architecture, and the engineers who are facilitating the mass adoption of RISC-V through customized silicon, design platforms and accelerators.

The seminar is free to attend and will include a broad spectrum of guest speakers, ranging from well-known professors at Indian institutes and research organizations to company founders and senior executives from the U.S. and India who are witnessing, first hand, the momentum of RISC-V and its impact on the worldwide semiconductor ecosystem.

Seating is limited, so please register online now to secure your spot using below link.

http://sifive-open-silicon-technical-symposiums.com/registration/

We look forward to seeing you there!

All the best and happy learning…