Really apologize for delay in discounts…

Published: Sat, 06/30/18

I guess you have requested a couple of times in last week for coupons, and I really apologize as I was not able to release sufficient coupons as got busy with DAC 2018 (a detailed post coming soon, stay tuned). Let me give you an update about all webinars we did this year –

We started this year with a promising timing-eco webinar (which will have labs very soon), and here’s the link to that webinar:

https://www.udemy.com/vsd-timing-eco-engineering-change-order-webinar/?couponCode=LASTDAY_DISCOUNT

This webinar was followed-up by Physical design webinar by Rajeev Srivastava, who headed a start-up, few years back and now an experienced Physical designer in NXP. Here’s the link for the same:

https://www.udemy.com/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=LASTDAY_DISCOUNT

Next, we introduced a new technology, a new language (TL-Verilog) with Steve Hoover, an Intel veteran and as I have seen in DAC, this will be probably a replacement to System Verilog, very soon. So, learn it today and be ready for the future, using below webinar link: We taken an example of RISC-V pipe-line

https://www.udemy.com/vsd-pipelining-risc-v-with-transaction-level-verilog/?couponCode=LASTDAY_DISCOUNT

Now here, just before my conference to China, we released and introduced “cloud-based” platform with Tim Edwards, ex-Analog devices, to do SOC design and Physical design of RISC-V core, right specifications to Layout, and is a perfect fit for your today’s job requirements. Below are the links to those webinars:

https://www.udemy.com/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=LASTDAY_DISCOUNT

https://www.udemy.com/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=LASTDAY_DISCOUNT

Welcome to future – Machine Learning in EDA/CAD – this topic was the key highlight of DAC, and we are proud to have an introductory course about this by Rohit Sharma, who is a Machine Learning expert. Here’s the link for the same:

https://www.udemy.com/vsd-machine-intelligence-in-eda-cad/?couponCode=LASTDAY_DISCOUNT

Clifford Wolf, who is popularly known for his open-source synthesis tool ‘Yosys’ had done a RTL QnA webinar and here’s the link for the same. If you hear his story, I am very sure, you will be inspired:

https://www.udemy.com/vsd-rtl-synthesis-qa-webinar/?couponCode=LASTDAY_DISCOUNT

Finally, we ended second quarter of this year with a webinar from Prof. Tsung-Wei Huang (UIUC, USA) on Distributed Timing Analysis – A hot topic and knowledge base for people doing STA for millions of instances count design. Here’s the link for the webinar:

https://www.udemy.com/vsd-distributed-timing-analysis-within-100-lines-code/?couponCode=LASTDAY_DISCOUNT

Another good news about all the above advanced webinars is, you would need some basics to start with, and that, you will find in my below links (Take courses in below order):

RISC-V ISA (hot topic of DAC):

https://www.udemy.com/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=LASTDAY_DISCOUNT

TCL Programming (hot topic and most useful for working freshers/working professionals):

https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert/?couponCode=LASTDAY_DISCOUNT

https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=LASTDAY_DISCOUNT

Physical design flow:

https://www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=LASTDAY_DISCOUNT

Clock tree synthesis:

https://www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=LASTDAY_DISCOUNT

https://www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=LASTDAY_DISCOUNT

Signal integrity:

https://www.udemy.com/vlsi-academy-crosstalk/?couponCode=LASTDAY_DISCOUNT