As you might be knowing by now, I am an invited speaker at RISC-V workshop happening at IIT Madras, Chennai, I thought of sending below registration link to you, as this would be an excellent opportunity for me to meet you in person.

My talk is on VLSI floor-planning for optimum power, performance area and I have used SiFive E-series as testcase, using opensource EDA tools. Above image shows the detailed description of my talk

In case you would like to attend the RISC-V workshop, below is the link to register, which has details about my talk as well:

Registering using above link gives you access to 2-day (18-19 July) workshop including my talk. If you are a student, make sure you take advantage of student discount. If you are in and around Chennai, this would be a great opportunity to meet as we have been only connected online

You might want to forward this invitation to your friends in and around Chennai who would be interested to attend this workshop.

Please ignore/decline this invitation if you are not around