So, start with any design, say a RISC-V core (since I have readymade courses on RISC-V), understanding about design components, like, SPI module, UART, SRAM, pad-frames, voltage domains, and assembling parts in verilog module like top level connections like pads, level shifters, multiplexers and small testbench suite. Here’s a full-fledged course on the same:

Theory & Labs:

https://www.udemy.com/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=PREP_INTERVIEW

https://www.udemy.com/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=PREP_INTERVIEW

Next, move to pre-layout timing analysis and Floorplanning – By this, I mean setup/hold analysis, report nworst, timing_qor, analysis_coverage in clock ideal mode, aspect ratio, utilization factor, power planning, pre-placed cell tap cell, macro, memory/IP placement. And here are the courses for the same:

Theory:

https://www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=PREP_INTERVIEW

Labs:

https://www.udemy.com/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=PREP_INTERVIEW

Then, continue with placement, clock tree synthesis, routing and crosstalk/signal integrity – This involves placement STA with clock ideal, CTS quality check – skew, pulse width, duty cycle, latency, Routing quality check – signal integrity, delta delay, glitch. Below are the courses for same:

Theory & Labs:                        

https://www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=PREP_INTERVIEW

https://www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=PREP_INTERVIEW

https://www.udemy.com/vlsi-academy-crosstalk/?couponCode=PREP_INTERVIEW

Next comes Post-layout STA – Like types of setup/hold checks – reg2reg and IO, clock gating, recovery/removal, data-to-data, latch (time borrow/time given), Need of library, advanced ccs/ecsm concepts, variation (OCV, AOCV, SOCV in brief). Below are theory and lab courses for the same:

Theory:

https://www.udemy.com/vlsi-academy-sta-checks/?couponCode=PREP_INTERVIEW

https://www.udemy.com/vlsi-academy-library-characterization-part-1/?couponCode=PREP_INTERVIEW

Labs:

https://www.udemy.com/vlsi-academy-sta-checks-2/?couponCode=PREP_INTERVIEW

https://www.udemy.com/vsd-library-characterization-and-modelling-part-2/?couponCode=PREP_INTERVIEW

And finally, engineering change order (ECO) – Review impact of ECO on power, performance and area, Margin based and slack based ECO for selective endpoints, PBA based ECO and leakage-recovery, Hierarchical and Physical aware ECO and bottle neck analysis. Below is the final course:

Theory:

https://www.udemy.com/vsd-timing-eco-engineering-change-order-webinar/?couponCode=PREP_INTERVIEW

Bonus Course – TCL programming: This skill is like a bonus and a favorite question of all interviews “Do you know TCL programming?”

Take up below 2 courses on TCL programming and your answer to above query will a “Yes”

Theory and Labs:

https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert/?couponCode=PREP_INTERVIEW

https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=PREP_INTERVIEW

All above courses, if spent atleast 8-hour per day, should not take more than 5-days for you to finish. And, literally, time’s running out. Interviews are closing by, spend some time now, focusing and revising the entire curriculum for next 5-days, I can guarantee you, you would come out as a winner…

All the best for your interviews and happy learning….