Please join me to congratulate below participants for successfully building a "Frequency Counter chip" and all using open-source EDA PNR tools. I can guarantee you, this challenge is going to take below participants to even greater heights, because very few people in whole VLSI industry are doing what they did, and very few people in the industry know what they know. That makes all 4 of them 'unique'. Really proud and congratulations from entire VSD and eFabless team.

Wish you all the best. I will reach out to you separately for a paper submission plan in VSDOpen online conference and Semicon Conference happening in Shanghai, China, next year. Let's show the whole world what you are capable of

In-fact, from the responses we received from above participants, its really worth a look of the power of open-source EDA tools and I am sure, this is just the beginning. The "full physical design flow" webinar that we conducted on 2nd June, using all opensource tools, can be found in below link-