[LAST 36 HOURS] PicoSoC Physical Design Webinar agenda

Published: Thu, 05/31/18

We must go through a lot of stuff about how we do floorplan. The below is how it looks like, after you have finished everything, but how did we start – that’s important. At the bottom left, you will find a cell – raven SPI, the block that will be used for labs. Its an abstract view, which we pull from top in to the chip core area

To create the abstract views, there will be standard scripts available on efabless platform, there will be a system which would be there in place, which will allow anyone to use the script. In essence, what its doing is, its bringing up MAGIC (opensource VLSI layout tool) and saying “lef write”. Once you have all LEF’s, below is how the chip will look like:

We will discuss about routing and, there is also a way, where you can trace your power (or ground) network for the whole chip. Below is how we traced a ground network through the hierarchies

And finally, you can create your own logo as shown below, on your own chip, which says, you made it and you did it…Now what you see above is a full-fledged micro-processor and what you see below is your name embedded in your chip

Aren’t these some of the coolest topics you will learn in physical design? Learn more in our upcoming webinar on “SoC Reference Design of the PicoRV32 RISC-V Microprocessor”. Here’s the link to enroll:[LAST 36 HOURS]

https://www.vlsisystemdesign.com/upcoming-event/

Note: Once you enroll, please email me the confirmation ticket on kunalpghosh@gmail.com and claim 1 of below courses for FREE

1. VLSI – Essential concepts and detailed interview guide

2. VSD – Clock tree synthesis – Part 1

3. VSD – Signal Integrity

4. VSD – RISCV: Instruction set architecture – Part 1a

5. VSD – Physical design flow

6. VSD – Circuit design and SPICE simulations – Part 1

7. VSD – Static timing analysis – Part 1

8. VSD – Circuit design and SPICE simulations – Part 2

9. VSD – Clock tree synthesis – Part 2

10. VSD – Custom layout

11. VSD – Static timing analysis – Part 2

12. VSD – Library characterization and modelling – Part 1

13. VSD – Static timing analysis Webinar

14. VSD – TCL programming – Part 1

15. VSD – TCL programming – Part 2

16. VSD – RISCV: Instruction set architecture – Part 1b

17. VSD - Timing ECO Webinar

18. VSD - Physical design webinar

19. VSD - Pipe-lining RISC-V using TL-verilog

20. VSD - SOC Design webinar

21. VSD - Machine Intelligence in EDA/CAD webinar

22. VSD - Library characterization and modelling - Part 2

23. VSD - RTL synthesis QnA webinar

24. VSD – Distributed STA