Note: Once you enroll, please email me the confirmation ticket on kunalpghosh@gmail.com and claim 1 of below courses for FREE

1.       VLSI – Essential concepts and detailed interview guide

2.       VSD – Clock tree synthesis – Part 1

3.       VSD – Signal Integrity

4.       VSD – RISCV: Instruction set architecture – Part 1a

5.       VSD – Physical design flow

6.       VSD – Circuit design and SPICE simulations – Part 1

7.       VSD – Static timing analysis – Part 1

8.       VSD – Circuit design and SPICE simulations – Part 2

9.       VSD – Clock tree synthesis – Part 2

10.   VSD – Custom layout

11.   VSD – Static timing analysis – Part 2

12.   VSD – Library characterization and modelling – Part 1

13.   VSD – Static timing analysis Webinar

14.   VSD – TCL programming – Part 1

15.   VSD – TCL programming – Part 2

16.   VSD – RISCV: Instruction set architecture – Part 1b

17.   VSD - Timing ECO Webinar

18.   VSD - Physical design webinar

19.   VSD - Pipe-lining RISC-V using TL-verilog

20.   VSD - SOC Design webinar

21.   VSD - Machine Intelligence in EDA/CAD webinar

22.   VSD - Library characterization and modelling - Part 2

23.   VSD - RTL synthesis QnA webinar

24.   VSD – Distributed STA