Just to give you some background, picoSoC is an example SoC using PicoRV32, and PicoRV32 is a size-optimized RISC-V CPU which implements RV32IMC instruction set architecture.

Now, while I was working as Physical design engineer in my first design company, I had always pushed to spend around 30% of design cycle on having good floor-plan, because a good floor-plan will always save your design-cycle run-time, and give you far better PPA (power, performance, area)

We are starting to implement PicoSoC hierarchical physical design in about a week (more to come on this later), so pour in your ideas to make the below floor-plan a better one. You can comment or email your ideas to my personal email id kunalpghosh@gmail.com

I have made sure, the logical routes don't go over the top of any blocks. Be prepared for a follow-up webinar on this topic. First SoC planning webinar is already been done by Tim Edwards and can be found in below link:

https://www.udemy.com/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=PART_ONE_COMPLETE