We did another dry run, where we selected 3 timing views and distributed each timing view over different machines parallely and benchmarked the results in terms of run-time and CPU
usage with standalone run of all timing views. The results are something which displayed the power of distributed STA for different views parallely.
In my opinion, the learning cycle completes only when you do it on your own and review the engine which does it for you. This is what differentiates a normal STA engineer from an expert. This knowledge is what distinguishes a normal engineer to a well-equipped engineer when applying for
jobs. And you can't be lucky enough to get all knowledge by just the click of a button
Do you want to be called as an expert? Do you want to be differentiated from others in your work and interviews? If yes, here's the link to enroll in the webinar happening few hours from now: [Ticketing closes in 6 hours]
1. VLSI – Essential concepts and detailed interview guide
2. VSD – Clock tree synthesis –
Part 1
3. VSD – Signal Integrity
4. VSD – RISCV: Instruction set architecture – Part 1a
5. VSD – Physical design flow
6. VSD – Circuit design and SPICE simulations – Part 1
7. VSD – Static timing analysis – Part 1
8. VSD – Circuit design and SPICE
simulations – Part 2
9. VSD – Clock tree synthesis – Part 2
10. VSD – Custom layout
11. VSD – Static timing analysis – Part 2
12. VSD – Library characterization and modelling – Part 1
13. VSD – Static timing analysis Webinar
14. VSD – TCL programming – Part 1
15. VSD – TCL programming – Part 2
16. VSD – RISCV: Instruction set
architecture – Part 1b
17. VSD - Timing ECO Webinar
18. VSD - Physical design webinar
19. VSD - Pipe-lining RISC-V using TL-verilog
20. VSD - SOC Design webinar
21. VSD - Machine Intelligence in EDA/CAD webinar
22. VSD - Library characterization and modelling - Part 2
23. VSD - RTL synthesis QnA
webinar
