RTL Synthesis QnA webinar by Clifford Wolf

Published: Tue, 05/01/18

Our next webinar is slightly different one. It’s a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of ‘Yosys’ which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Now to make this webinar a successful one, we need your help.

Clifford will be answering top 25 queries on RTL synthesis. This is your chance to draft your queries using below link, which will get registered with me and my team. We will review all queries, and TOP25 will be selected to be answered in webinar. Entry to this 2-hour webinar is FREE, recording is paid. So, buy it, if you like it.

https://www.vlsisystemdesign.com/upcoming-event/

This webinar opens 2 new opportunities, one – a chance to interact with architect of Synthesis, two – a chance to get your question in TOP25 list. Since we have already started receiving queries, make sure you draft challenging queries.

Suggestion would be to check if your query is already answered anywhere in google. If not, post that query in above link. TOP25 are directly eligible for certificates from our company “VSD Corp. Pvt. Ltd.” All the best and happy learning.

Note of Appreciation - I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course