For the best chip in terms of power, performance and area, you need to have robust timing, power and noise analysis. For all kinds of analysis, you need to have robust libraries. That's exactly what this webinar is about. Its exciting to learn what goes behind the making of low power chip, or high
performance chip.
All these and many more to learn in below 4-hour webinar. Last 36 hours to enroll and claim 1 out of my 21 courses for FREE. Here's the registration link:
Its easy. You need to enroll in webinar using above link. After webinar, I will send you an email which
has the list of below courses out of which you can claim 1 course for FREE.
List of courses
1. VLSI - Essential concepts and detailed interview guide
2. VSD - Clock tree synthesis – Part 1
3. VSD - Signal Integrity
4. VSD - RISCV: Instruction set architecture – Part
1a
5. VSD - Physical design flow
6. VSD - Circuit design and SPICE simulations – Part 1
7. VSD - Static timing analysis – Part 1
8. VSD - Circuit design and SPICE simulations – Part 2
9. VSD - Clock tree synthesis – Part 2
10. VSD - Custom layout
11. VSD - Static timing analysis – Part
2
12. VSD - Library characterization and modelling – Part 1
13. VSD - Static timing analysis Webinar
14. VSD - TCL programming – Part 1
15. VSD - TCL programming – Part 2
16. VSD - RISCV: Instruction set architecture – Part 1b
17. VSD - Timing ECO webinar
18. VSD - Physical design webinar using EDA tool ‘Proton’
19.
VSD - Pipelining RISC-V with transaction level verilog
20. VSD - Making the Raven Chip: How to design a RISC-V SoC
21. VSD - Machine intelligence in EDA/CAD
All the best and I will see you on 28th April for Webinar
