Hi

Thank You if you have enrolled in this webinar which starts in next 16 hours...Just like you, even I am excited to meet you all in person in webinar. I am very sure, you will take away some real cool concepts on top level chip integration using Verilog and finally, build your own chip

If you haven't grabbed your tickets yet, this is one final call, before we close ticketing in next 13 hours. More-over, as you must have seen my previous posts, only 4 seats are left. Unfortunately, we cannot accommodate any more as it will load up our servers where you will be doing labs. So make it soon.

Here's the registration link:

You will be given assignments at the end of the day, which will be, again, in verilog. So we hope you learn and master verilog, and build real chips by the time webinar finishes. And this webinar is being designed in such a fashion, you don't need much per-requisites.

Also, by enrolling in this webinar, you can claim one of online udemy courses for FREE. So at the price of 1 you get 2...Pretty good deal you see...This offer is to encourage all of you to learn as much as you can in a short time, as placements are nearing and want you all to be prepared