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After a month's of hard-work on TL-Verilog webinar, and successfully delivering it, we just went to our review page, and found tons of reviews out of which I
grepped 4 shown in above image. This is what we call 'Judgement Day'. You are a better judge of our work, and I would like to "Thank You' for all the support you have been constantly providing for last couple of years
Below are the courses under which you can find all above reviews to check out by yourself:
Library Characterization:
Static Timing Analysis - Part 1:
Physical Design Flow:
Also, in case, you missed Steve's webinar due to GATE exams, here's a recorded copy of it:
Pipe-lining RISC-V with TL-verilog:
This is what I like about my job. I don't have one supervisor, I have many. I do have all of you looking at my work
and providing your honest review, without any 'no. of years of experience' barrier. Even though you might be a student or fresher or experienced, I work for all of you and I do wait for my "Performance appraisal" every month.
For us, every day is a "Judgement Day". And we love it...
