This is in reply to your query on the flow in which all my Udemy courses need to be taken. This is valid for next 6 hours, and I have arranged out of multiple requests received from people who missed earlier mails. Really apologize as this is the FINAL CALL for getting my courses at
$9.99/course.
Tips on order in which you need to learn VLSI and become a CHAMPION:
If I would had been you, I would had started with Physical Design and
Physical design webinar course where I understand the entire flow first, then would have moved to CTS-1 and CTS-2 to look into details of how the clock is been built.
Physical design:
https://www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=FOR_A_TIME
Physical design webinar:
https://www.udemy.com/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=FOR_A_TIME
Clock tree synthesis:
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=FOR_A_TIME
https://www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=FOR_A_TIME
Then, as you all know how crosstalk impacts functioning at lower nodes, I would gone for Signal Integrity course to understand impacts of scaling and fix
them.
Signal integrity:
https://www.udemy.com/vlsi-academy-crosstalk/?couponCode=FOR_A_TIME
Once I do that, I would want to know how to analyze performance of my design and I would have gone for STA-1, STA-2 and Timing
ECO webinar courses, respectively
Static timing analysis:
https://www.udemy.com/vlsi-academy-sta-checks/?couponCode=FOR_A_TIME
https://www.udemy.com/vlsi-academy-sta-checks-2/?couponCode=FOR_A_TIME
https://www.udemy.com/vsd-static-timing-analysis-sta-webinar/?couponCode=FOR_A_TIME
Timing ECO webinar:
https://www.udemy.com/vsd-timing-eco-engineering-change-order-webinar/?couponCode=FOR_A_TIME
Once you STA, there’s an internal curiosity which rises, and wants us to understand, what goes inside timing analysis at transistor level. To full-fill that, I would had taken Circuit design and SPICE simulations Part 1 and Part 2 courses.
Circuit design and SPICE simulations:
https://www.udemy.com/vlsi-academy-circuit-design/?couponCode=FOR_A_TIME
https://www.udemy.com/vlsi-academy-circuit-design-part2/?couponCode=FOR_A_TIME
And finally, to understand pre-placed cells, IP’s and STA in even more detail, I would have taken custom layout course and Library Characterization course
Custom Layout:
https://www.udemy.com/vlsi-academy-custom-layout/?couponCode=FOR_A_TIME
Library characterization - Part 1:
https://www.udemy.com/vlsi-academy-library-characterization-part-1/?couponCode=FOR_A_TIME
All of above needs to be implemented using a CAD tool and needs to be done faster, for which I would have written TCL or perl scripts. So for that, I would start to learn TCL-Part1 and TCL-Part2 courses, at very beginning or in middle
TCL Programming:
https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert/?couponCode=FOR_A_TIME
https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=FOR_A_TIME
Finally, if I want to learn RTL and synthesis, from specifications to layout, TL-Verilog Webinar and RISC-V ISA course will teach the best way to define specs for a complex system like
microprocessor