We recently did a very successful webinar with Steve Hoover on “Pipelining RISC-V using transaction-level verilog” on 10th Feb. It was very interactive and many of you were not able to join it due to GATE exams or international payment issues.
So, here’s the
recorded copy of the webinar pre-launched at 90% discount price (valid for next 7 hours):
I would say, you did miss the LIVE interaction with Steve and may be, next time, you should be looking forward to attend in person. We have uploaded 10 videos and will be uploading rest in a day or 2. Enjoy the webinar, just in the way we enjoyed it in LIVE session
All the best and happy
learning…
FYI:
I have been getting multiple request on order in which all my courses need to be taken. So here’s the list of courses (each at 90% discount, on the eve of new course launch) for (valid for next 7 hours):
Physical Design flow:
Physical Design webinar with EDA tool:
Clock tree synthesis:
Signal integrity:
Static timing analysis and webinar:
Timing ECO:
Circuit design and SPICE simulations:
Custom Layout:
Library characterization Part 1:
TCL programming:
RISC-V ISA:
VLSI Essential concepts and detailed interview guide:
If the above courses don’t make you an expert, I will refund all your money within 30 days of purchase. No questions asked…
