We are back with our 3^rd webinar of this year (10^th in series), and this is a complete breakthrough. Reason – In my RISC-V ISA part 1 Udemy course, we had promised to show you how to implement a computer architecture. One of the keys to have the fastest CPU is to have an exceptional Pipeline infrastructure for fetch, decode and execute instructions.

While, we all might or might not know how to implement the same in Verilog (or VHDL), they were designed for describing event-based simulators that model hardware behavior. Transaction-Level verilog, is specifically designed for modelling hardware. If you can read between lines, there’s lot of arguable differences in above statements.

So, you have something new to explore, something new to learn, something which will keep you ahead of time and other professionals. I welcome you to webinar on “Pipelining RISC-V with Transaction-Level Verilog” (designed for both students and professionals) with Steve (has about 18+ years of experience in field of verification and logic design) and Myself. Tools are available on cloud, which we will introduce at time of webinar, so you need not download and install anything.

Here’s the ticket link. Make sure you get one today itself, as tickets gets used up soon

And as any of my other webinars, I promise to make this the most interactive and successful one…All the best and happy learning…