Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser, probably Google Chrome?

How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”

Did this blog make you think? I encourage and welcome you to think in the right direction with experts from this field in my next webinar on “Pipelining RISC-V with Transaction-Level Verilog” on 10^th Feb’ 2018. Just like my any previous webinars, even in this one, you will be able to interact with industry experts directly

And this time, we have instructors all the way from Greater Boston Area, US, with more than 18+ years of experience in the field of “Logic Design and Verification”

All I can say is, me and participants who will be attending this webinar, will be “blessed”. I would re-iterate, just like my previous webinar emails, “recording is good, but LIVE is best”

Stay tuned for tickets link and more about this webinar!!!

Happy Learning…