As you know, we had conducted a worldwide Timing ECO webinar on 6th Jan, 2018, now please find the pre-launch of Timing ECO course. We have uploaded first 45 minutes, roughly about 5 videos, for initial launch, so that you receive your copy for just $10, and just for today (valid for next 6
hours)
With that said, I would have still suggested you to attend the LIVE
webinar, as there were many experts and LIVE QnA session with the experts. When freshers and professionals discuss issues with experts, its like a healthy discussion happening in any Semiconductor company and the experience was worth the effort and time spent
Anyways, if you had missed the LIVE version, no issues. There will be many more webinars on Physical Design, IR analysis and System Verilog being planned already in upcoming weeks.
Be a part of the webinar and get a chance to interact with industry experts LIVE.
“Nothing can beat their experience”
Thanks
Kunal
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Just a tip – Ideally, Timing ECO course should be taken in below order
- Physical Design - https://www.udemy.com/vlsi-academy-physical-design-flow/?couponCode=WEB_LAUNCH_UDEMY
- Clock tree synthesis – Part 1 - https://www.udemy.com/vlsi-academy-clock-tree-synthesis/?couponCode=WEB_LAUNCH_UDEMY
- Clock tree synthesis – Part 2 - https://www.udemy.com/vlsi-academy-clock-tree-synthesis-part2/?couponCode=WEB_LAUNCH_UDEMY
- Static timing analysis – Part 1 - https://www.udemy.com/vlsi-academy-sta-checks/?couponCode=WEB_LAUNCH_UDEMY
- Static timing analysis – Part 2
- https://www.udemy.com/vlsi-academy-sta-checks-2/?couponCode=WEB_LAUNCH_UDEMY
- Timing ECO - https://www.udemy.com/vsd-timing-eco-engineering-change-order-webinar/?couponCode=WEB_LAUNCH_UDEMY
If you are aware of 1) to 5) either on Udemy or from other sources, you can take up Timing ECO course directly, and get the best out of it
On that eve, I would also like to give away all my other courses at 90%
discount (a price which you will never find again). So, it might be a good idea to grab it today as it lasts for next 6hours
Signal integrity:
Circuit design and SPICE simulations – Part 1:
Circuit design and SPICE simulations – Part 2:
Custom Layout:
Library
characterization and modelling:
STA webinar:
TCL programming – Part 1:
TCL programming – Part 2:
RISC-V ISA – Part 1a:
RISC-V ISA – Part 1b:
Essential concepts and detailed interview guide:
