Did you know, margin based ECO saves lot of area and power?

Published: Wed, 01/03/18

Apart from margin based ECO, did you know there are other strategies of doing efficient ECO rather than regular ECO? This is what will differentiate you from others as a timing engineer. Join webinar on Jan 6th and explore some more techniques to do ECO

Seats are filling up fast, so if you haven't reserved your spot yet, here's your chance to do so

You have only 2 days to claim your FREE course

It’s simple. Below are the steps -

Enroll in webinar using the link http://go.eventshigh.com/85obz
Forward the event confirmation email at kunalpghosh@gmail.com, along with the name of course (from list at bottom of this message) which you need for FREE
You will receive a unique link from me, which will get you enrolled into your choice of course for FREE

Not only that, after successful completion of Timing ECO webinar on 6^th Jan, you also get a FREE video copy of the recorded webinar.

Isn’t that something great? All you need to do is, enroll in “Timing ECO webinar” on 6^th Jan using below link

http://go.eventshigh.com/85obz

"You attend, You learn and You earn" - It just can’t get easier than this…(one batch is full, second batch of 21 tickets, filling fast)

I will see you on 6^th Jan, 9am, LIVE ONLINE

FYI: You can claim 1 course for FREE from below list -

VLSI - Essential concepts and detailed interview guide
VSD - Clock tree synthesis - Part 1
VSD - Signal Integrity
VSD - RISCV: Instruction set architecture - Part 1a
VSD - Physical design flow
VSD - Circuit design and SPICE simulations - Part 1
VSD - Static timing analysis - Part 1
VSD - Circuit design and SPICE simulations - Part 2
VSD - Clock tree synthesis - Part 2
VSD - Custom layout
VSD - Static timing analysis - Part 2
VSD - Library characterization and modelling - Part 1
VSD - Static timing analysis Webinar
VSD - TCL programming - Part 1
VSD - TCL programming - Part 2
VSD - RISCV: Instruction set architecture - Part 1b