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This new course (yet to be uploaded) is in continuation with my previous course "VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.

All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course at-least 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture - An important one needed in today's fast changing computing world.

Here's the link of Part 1a course, in case you have missed it -

We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.

Watch the promo video for RISC-V ISA - Part 1b below...

Pre-launch link will be posted anytime soon...So Stay tuned...