We will also develop a command “read_sdc” which will take constraints in SDC format and convert it to an EDA tool format, whichever tool it may be. This command, which we are going to develop, has the capability to differentiate between bussed port and bit-blasted port, which is an important requirement to analyze
timing
Finally, we will find a way to get an output QOR in a horizontal or vertical format, whichever way you wish. To achieve the above tasks, its really very important to complete below course 100%
So get ready for another ride. I will keep you posted on the pre-launch of this course….Till then…Happy Learning…
PS : I got few 90% discount coupons for all my courses which is valid for next 6 hours from now, and here are the links. In case you have missed the
coupons in past, here’s your final chance to get them:
STA Webinar:
Library characterization and modelling – Part 1:
Static Timing Analysis:
Custom Layout:
Clock tree synthesis:
Signal Integrity:
Circuit design and SPICE simulations:
Physical design flow:
I will see you in class...Thank You
