For everyone, who has been aggressively working on (or will be working on) Physical Design and STA will need this book today or tomorrow. Why
is this important? Once your design is placed on chip, the real performance killer, especially for lower nodes, is parasitics.
To kill the killer, you need to know your killer. And there are very few or zero documents available on internet which explains SPEF format in detail as per latest IEEE standard. Now being an IIT Alumni and an active IEEE
member, I do read a lot of journals and papers from past 10 years
If you face issues downloading this book, please drop me an email
at kunalpghosh@gmail.com
