**Coming Soon**

Its been a real problem and pain for students, hobbyists, innovators and myself to realize their ideas using EDA tools due to 2 major reasons

1) Standard EDA license costs affordability

2) Ease of use for Open-source EDA tools

And I think, its time for me to go to the next level and solve this problem

After the huge success of our online VLSI courses using open-source tools, VSDSYNTH, our new product (currently in beta testing) is unique UI that will take in inputs in form of RTL netlist and read standard SDC format constraints. The UI will generate synthesized netlist and pre-layout timing reports, hereby giving you first hand information on the quality of your RTL design

Currently, few SDC constructs are supported. VSDSYNTH uses open-source tools yosys and opentimer in the back-end to generate reports, but all calculations is being done by the below UI. So stay tuned, and very soon you all will access to this UI.

Till then....Happy Innovating and Happy Learning.....