And once you have these values of dc_current, you just need to refer to timing model of that CCC and compute the delay change…Wasn’t that a very difficult task, just made easy, by use of images?
I believe your job as an STA engineer or Physical design engineer is incomplete without the concepts of libraries , which I quote as ‘the
heart of STA, PNR, CTS and Crosstalk’, in my course on “Library characterization and modelling – Part 1”
You can imagine, how exciting and easy I have made this course. Your job is to just listen and everything else has been taken care of…For more, subscribe my course at just $11 for next 1 day, and here’s the link:
Enter now, and I will see you in class…Till then, happy learning!!
FYI :
All my courses are available at $11 for next 1 day…Use the below links to enroll yourself in the class, and welcome to my community….
(List of supporting courses for Library
Characterization course):
Static timing analysis – Part 1:
Static timing analysis – Part 2:
Circuit design and SPICE simulations – Part 1 (Mandatory, no exceptions):
Circuit design and SPICE simulations – Part 2 (Mandatory, no exceptions):
Custom layout:
(Other industry oriented courses)
Physical design flow:
Clock tree synthesis – Part 1:
Clock tree synthesis – Part 2:
Signal integrity:
VLSI – Essential concepts and detailed interview guide:
