Are you analyzing noise? Then meet me, I am CCC

Published: Wed, 03/22/17

A channel connected component (CCC).

For some reasons, I feel my friends in CAD company or my leads are not able to introduce me very well to you.
So here I am, like an open book, fully simplified. Glad to meet you

Myself, Channel Connected Component or CCC as I am being called by noise analysis engine architects. And to identify me in a circuit, you just need to know, I have 3 rules as shown in below image:
My first rule – I receive my inputs only at my gate terminal of transistor that’s inside me

My second rule – I send outputs only to gate terminal of transistors lying outside my territory. I can also send outputs to a Primary Output of a logic device

My third rule – I have top notch connections to VDD and/or GND

Now I think, that’s not enough unless I show up myself to you inside a flip flop. So meet me in below image. I am sitting inside every logical gate, like Flipflop below:
Now my friend ‘inverter’ is not called as a CCC, unless he follows the rules I just mentioned above. Sometimes, he does follows all rules and gets recognized as a CCC. So, in above image, some of my ‘inverter’ friends do follow the rules, while few of them doesn’t. The highlighted one’s are me, being categorized as CCC.

I do have some more friends like me inside above flipflop. I am shading them as blue in below image, for a reason.
But, currently I am more concerned about you characterizing and modelling noise for a flipflop, so I am only worried about the one’s shaded in Green, as the one’s shaded in blue is being taken care by Custom Layout engineers

Now, if you want to analyze noise, you just need to model the noise on my boundaries, the one’s in Green shaded, and you noise analysis will be taken care of.

This brings me to very important point that the gates are being categorized on my presence. If I am present multiple times as shown in above image, including green and blue shaded area, such gates (like flipflops) are being categorized as multi-stage cells
For gates like inverter, I am alone, as the inverter, by design, follows all rules which I want him to follow to be categorized as CCC. So inverters are being categorized as single-stage cells, while gates like NAND or AOI, where I am present twice, they are being categorized as 2-stage cells.

People don’t talk about me much, and so I am being neglected, but not anymore, and Thanks to Kunal for bringing me on this platform before all of you…”The most important thing in communication is hearing what isn’t said” – Peter Drucker

There’s a lot being talked about me in Kunal’s course on Library characterization and modelling – Part 1. You just might want to have a look at that course and hear a lot about me…

I will meet you in class, till then … happy learning…

FYI:
Get all my courses at $11 using below discount coupon links, which is valid till tomorrow midnight 11:59pm IST

Library characterization and modelling – Part 1:

Static timing analysis – Part 2:

Custom Layout:

Clock tree synthesis – Part 2:

Circuit design and SPICE simulations – Part 2:

Static timing analysis – Part 1:

Circuit design and SPICE simulations – Part 1:

Physical design flow:

Signal integrity:

Clock tree synthesis – Part 1:

VLSI – Essential concepts and detailed interview guide: