For gates like inverter, I am alone, as the inverter, by design, follows all rules which I want him to follow to be categorized as CCC. So inverters are being categorized as single-stage cells, while gates like NAND or AOI, where I am present twice, they are being categorized as 2-stage cells.
People don’t talk about
me much, and so I am being neglected, but not anymore, and Thanks to Kunal for bringing me on this platform before all of you…”The most important thing in communication is hearing what isn’t said” – Peter Drucker
There’s a lot being talked about me in Kunal’s course on Library characterization and modelling – Part 1. You just might want to have a look at that course and hear a lot about me…
I will meet you in
class, till then … happy learning…
FYI:
Get all my courses at $11 using below discount coupon links, which is valid till tomorrow midnight 11:59pm IST
Library characterization and modelling – Part 1:
Static timing analysis – Part 2:
Custom Layout:
Clock tree synthesis – Part 2:
Circuit design and SPICE simulations – Part 2:
Static timing analysis – Part 1:
Circuit design and SPICE simulations – Part 1:
Physical design flow:
Signal integrity:
Clock tree synthesis – Part 1:
VLSI – Essential concepts and detailed interview guide: