Hi

If you’ve ever watched a clean STA report collapse after silicon comes back—or seen “mysterious” hold failures that your corner runs didn’t predict—this post is for you. The culprit is almost always the same: process variation at the device level quietly reshaped your delay distribution. If you don’t speak the language of CMOS physics, you’re flying blind.

This image is not AI generated :)

Our upcoming online program, “CMOS Circuit Design & SPICE Simulation using Sky130 Technology”, shows you how device physics drives timing—and how to build margins that stand up in the lab, not just in the tool. Only two cohorts remain this quarter, and we expect heavy demand. Details and registration:
https://www.vlsisystemdesign.com/cmos-circuit-design-spice-simulation-using-sky130-technology/

Why device physics decides your timing fate

Process variation → device variation → cell delay spread → path timing spread → STA guardbands.
That chain is the whole story.

• Process variation: non-uniform gate oxide growth, line-edge roughness, channel length/CD, random dopant fluctuation, stress/strain, contact resistance.
• Device variation: threshold VTV_TVT​, mobility μ\muμ, oxide capacitance CoxC_{ox}Cox​, series resistance Rs/RdR_s/R_dRs​/Rd​.
• Delay impact: inverter/FO4 delay ~ Cload⋅VDDIon\frac{C_{load} \cdot V_{DD}}{I_{on}}Ion​Cload​⋅VDD​​. Changes in VTV_TVT​ and μ\muμ perturb IonI_{on}Ion​, so the mean shifts and the sigma widens.
• Path/clock impact: chains of inverters/buffers accumulate variation; global vs. local components create correlation structures across the chip.

STA must then translate that physics into corners, derates, and uncertainty. Miss the physics and you’ll either over-guardband (area/power bloat) or under-guardband (silicon escapes).

This image is not AI generated :)

How variation shows up in STA (and why it surprises people)

• PVT corners capture systematic shifts (fast/slow, VDD ±, temperature). They don’t capture within-die randomness.
• OCV/AOCV/POCV model on-chip variation with path-depth and distance sensitivity. Your ±derates are proxying for real device scatter.
• LVF (Liberty Variation Format) and SSTA inject sigma/mean into timing arcs to better track distributions.
• CRPR (Clock Reconvergence Pessimism Removal) tries to not double-charge correlated variation.
• Setup/Hold asymmetry: local skew + random cell delay → hold breaks first (especially at cold/fast corners). Clock pull-in/push-out is a direct consequence of the same device physics.

If your mental model stops at “use these derate tables,” you’ll chase violations symptom-by-symptom. If you can map derates back to Vt​, μ, LeffL​, and R/C variation, you can predict where violations will appear—and fix the real cause.

A taste of what you’ll do in the course

This is a hands-on, online course using Sky130 so you can see and measure the physics yourself.

1. Device-to-delay lab
   1. Build an inverter chain and sweep model parameters (e.g., VTV_TVT​, LLL, RcontactR_{contact}Rcontact​).
   2. Observe how I ⁣− ⁣VI\!-\!VI−V changes translate to FO4 delay shifts.
   3. Extract delay distributions with Monte Carlo and visualize mean/σ.
2. From SPICE to STA intuition
   1. Map distribution tails to OCV/AOCV/POCV derates.
   2. See why the same sigma gives different risk for short vs. deep paths.
   3. Understand when CRPR meaningfully reduces pessimism (and when it doesn’t).
3. Corner strategy that reflects physics
   1. Select PVTs that bound systematic variation without exploding runtime.
   2. Add clock uncertainty rooted in jitter + variation, not folklore numbers.
   3. Build a hold-first closure checklist for fast-silicon surprises.
4. Engineering decisions, not superstition
   1. How much margin is “enough”? Use sigma-to-fail math, not guesswork.
   2. Where buffers help (and where they amplify variation).
   3. When to invest in LVF/SSTA vs. well-tuned AOCV.

Who should join

• STA/PD engineers who want fewer late surprises and smaller guardbands.
• Circuit/Library engineers who want their cells to time like they simulate.
• Students and career-switchers aiming for timing sign-off roles with real-world intuition.

Prerequisites: Basic CMOS and SPICE familiarity is helpful; we cover the essentials needed for the labs.

What you’ll take away

• A grounded understanding of how Vt​, μ, Cox​, Leff​, and contacts shape timing.
• The ability to read a derate table and say what device physics it implies.
• A concrete workflow to choose corners, uncertainties, and derates that are tight but safe.
• Reusable Sky130 SPICE setups you can extend for your own experiments.

Cohort details and registrations

• Format: 100% online, cloud-based recorded sessions with hands-on labs.
• Capacity: No upper cap on registrations.
• Availability: Only two cohorts left this quarter—once they start, the next window is next quarter.

Secure your spot now:
Register here → https://www.vlsisystemdesign.com/cmos-circuit-design-spice-simulation-using-sky130-technology/

If you want your STA to survive first silicon, start where timing truly begins: the transistor. Join us and turn device physics into timing confidence.