Hi

Every “semiconductor powerhouse” story starts at the same place: the transistor. If we want a workforce that can design reliable chips, close timing at scale, and build for harsh real-world conditions, we must anchor skilling at CMOS device physics - not just at RTL or system level.

Why this matters now

• The toughest design problems—power leakage, variability, margins, aging—are device-level first, and only then circuit/system-level.
• Teams that truly understand Id–Vg, gm, Vt, subthreshold slope, capacitances, PVT corners, BTI/HCI and noise margins make faster, better trade-offs in architecture, libraries, analog blocks, and sign-off.
• A talent pipeline grounded in transistor behavior scales across fabs, design houses, and EDA - exactly what India needs to climb from “adopter” to “leader.”

Take action at the ground level
We’ve designed a 10-day, hands-on workshop using the open-source SKY130 node that turns device physics into practical design skill—fast. Participants:

• Model and characterize MOSFETs (Id–Vds/Id–Vgs, velocity saturation, Vdsat).
• Build & size CMOS inverters, extract VTC, compute Vm, and optimize NMH/NML for robustness.
• Run transient delay and dynamic power analysis, then sweep VDD from 1.8 V to sub-1 V to see real trade-offs.
• Stress designs across TT/SS/FF corners and derive guard-bands for yield.
• Package results into reusable SPICE decks that dovetail with OpenLane/VSDFlow for RTL-to-GDS hand-off.

Outcomes you can hire and ship on

• Engineers who can explain why a path fails, not just that it fails—because they can map waveforms back to transistor behavior.
• Library/cell designers who tune (W/L) and thresholds for power-performance-area, with data—not guesswork.
• A pathway from device physics → cell design → sign-off that compresses iteration time and improves first-silicon confidence.

Let’s build from the bottom up - so we can lead at the top.

Best regards,

Kunal Ghosh