Hi

I’m excited to share an infographic we’ve just released that walks you through the three critical stages of modern digital design with Verilog on SKY130 technology: Behavioral RTL, Gate-Level Netlist, and Timing Optimization. Take a moment to study it, then hit “reply” and let me know which stage intrigues you most—just reply with A, B or C. I’ll gather your responses and address the top questions in my next update.

This feedback loop reflects exactly how we teach in our hands-on course, “RTL Design Using Verilog with SKY130 Technology.” We don’t stop at code examples—you’ll learn to think like a top-tier semiconductor engineer, seeing how synthesizable RTL feeds into gate-level verification and ultimately into timing-closure strategies that drive real-world tapeouts.

There are only four cohorts left and registration closes in 12 hours. If you’ve been waiting for the right moment to deepen your RTL-to-tapeout skill set, now is it.

Secure your spot here:
https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/

I look forward to your reply - let me know A, B or C - and to seeing you in the course.