Hi
Only 15 hours left to secure your spot in the TCL Workshop!
If you’ve ever wondered why TCL is the oxygen that runs VLSI and Semiconductor companies, this workshop is your answer. From
automating design flows to enabling seamless interaction with EDA tools like Yosys, TCL is the unsung hero behind every successful chip design.
What You’ll Achieve
By the end of this workshop, you’ll build a command-line utility (e.g., vsdsynth) that:
- Reads a CSV input from the shell and converts it into synthesis-ready
formats.
- Generates dynamic TCL scripts to automate timing constraints (SDC) and synthesis flows.
- Integrates with Yosys, the open-source synthesis engine, to transform RTL code into gate-level netlists (see example below!).
Check out the amazing outcomes from past participants here: GitHub Repository.
Why TCL is Indispensable in VLSI
The attached workflow snippet highlights TCL’s critical role:
- Task Automation:
- Convert CSV inputs to TCL scripts for synthesis.
- Automate SDC timing constraints generation.
- Feed data into Yosys to synthesize RTL modules (like the
Verilog memory block shown below) into logic gates.
- End-to-End Flow:
- Design RTL (e.g., memory with synchronous read/write).
- Synthesize using Yosys (INVX1, NAND2X1, DFFPOSX1 cells).
- Generate gate-level netlists for prototyping.
Without TCL, this entire pipeline—from design to synthesis—would collapse. TCL is the glue that binds
open-source EDA tools, enabling rapid iteration and scalability in semiconductor projects.
Workshop Highlights
- Hands-on tasks: Build a toolchain for digital design automation.
- Real-world RTL example: Design and synthesize a memory block (Verilog code provided!).
- Gate-level netlist mastery: Understand how synthesis translates RTL into logic gates.
Don’t miss this chance to add TCL automation to your skillset!
Register Now: TCL Workshop Link - https://www.vlsisystemdesign.com/tclworkshop/
Deadline: Registration closes in 15
hours.
Best regards,
Kunal Ghosh
Founder
VLSI System Design (VSD)
