Dear RISC-V and non-RISC-V Participants,
As we prepare to close registrations for the RISC-V MYTH workshop (link) in 7 hours,
we want to extend a heartfelt thank you to all of you who have been part of our journey over the last 5 cohorts. It has been an absolute pleasure interacting with this vibrant community of learners and innovators!
What’s Next After RISC-V Core Implementation?
Now that you’ve mastered RISC-V core design, the next logical step is to test your RISC-V core on real
hardware!
- VSDSquadron FPGA Mini (link): Deploy your RISC-V core on FPGA and validate it using our open-source framework (GitHub link).
The Skill
That Keeps You Relevant: Linux & TCL
To thrive in the VLSI and RISC-V industries, Linux and TCL are non-negotiable skills. From automation to tool flows, TCL scripting is the backbone of every VLSI engineer’s workflow. Even leadership roles demand proficiency here!
- TCL Workshop (link): Build this foundational skill to stay ahead in your career.
Final Call for RISC-V MYTH
If you’ve been waiting to join the RISC-V MYTH workshop, this is your last chance! Registrations close in 7 hours.
Once again, thank you for being part of this journey. Let’s keep pushing boundaries in VLSI and RISC-V!
Best regards,
Kunal Ghosh
VLSI System Design
P.S. Questions about FPGA labs, TCL, or future cohorts? Hit reply - we’re here to help!
