Hi

If you like small, readable cores you can actually reason about, the RISCV_MYTH arc is a neat sprint: start with C (sum 1..N), link a hand-rolled RV32I loop in load.S via the standard ABI, then hop into TL-Verilog for comb/seq exercises before wiring up decode. By Day 5 you’ve got a minimal RV32I with ~5 logical stages (@0..@5), clean PC update for JAL/JALR and the full branch set, LW/SW, and the usual ALU ops—kept intentionally spartan so waveforms stay legible.

Hazards are handled with basic forwarding and simple load-use care; memory is a single-port SRAM-like path good enough for lab validation. The repo’s tiny in-mem program (“sum 1..9”) closes the loop so you can watch fetch→WB do exactly what you expect. If you want to reproduce the C/ASM step fast:
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 1ton_custom.c load.S -o sum.elf (then run on Spike/QEMU/Renode).

This is a last-chance invite: the final Q3 MYTH cohort closes tonight, August 3, 2025 at 11:59 PM IST—about 14 hours left. It’s ~30 hours, mentor-led, end-to-end, and sets you up to bolt on M-extension, a tiny predictor, or caches without drowning in scaffolding.

Register: https://www.vlsisystemdesign.com/riscv-based-myth/

Best regards,
Kunal Ghosh