Hi

If the RISCV_MYTH repo sparked your curiosity, this is your last chance (this quarter) to learn and implement the whole stack end-to-end in our guided RISC-V MYTH (Microprocessor for You in Thirty Hours) workshop.

What you’ll build in ~30 hours

• Write portable C and RV32I assembly, and link them.
• Design in TL-Verilog: combinational/sequential logic, clean pipelines.
• Implement a minimal RV32I core with decode, ALU, branches/jumps, load/store, and basic bypassing.
• Simulate on Makerchip with waveforms and step-through debug.
• Validate with real programs (e.g., sum 1..N), and understand how instructions flow through the pipeline.

Why join

• Structured labs + mentor support + ready scaffolds from the repo.
• Clear outcomes you can demo, publish, and extend to FPGA later.
• Ideal for students, embedded devs, and VLSI/FPGA beginners who want ISA-level insight fast.

Deadline
Registration for the final Q3 cohort closes 11:59 PM IST, August 3, 2025. Seats are limited.

Register Now -> https://www.vlsisystemdesign.com/riscv-based-myth/

Best Regards,
Kunal Ghosh, Founder

VLSI System Design (VSD)

P.S. Share this with a friend who’s RISC-V-curious—this cohort is the last for the quarter.