Hi

Think your Verilog skills are job-ready? Let’s be brutally honest:
Academic Verilog ≠ Silicon-Proven RTL.

Most courses teach you to write code that simulates. This workshop teaches you to write code that builds physical chips.

Why Industry Ignores "Perfect" College Projects

1. The PDK Reality Check
   College labs: Simulate idealized modules.
   Industry: Designs must obey manufacturability rules from Day 1.
   Our start line: You’ll work with SkyWater SKY130 PDK – the same open-source kit used by Google, Efabless, and NASA. No hypotheticals.
2. Synthesis: The Great Filter
   Ever written "correct" Verilog that synthesized into garbage gates?
   This course kills that disconnect. You’ll:
   1. Craft RTL that survives synthesis
   2. Run Yosys flows mapping to standard cells
   3. See your code morph into physical gates before your eyes
3. The Tools Myth (Busted)
   "Need expensive licenses to learn?"
   Our weapon of choice: Icarus Verilog + GTKWave + Yosys
   Zero-cost. Industry-grade results.

This Isn’t a Course. It’s an Apprenticeship.

Why GitHub Repos ≠ Readiness (And What Actually Works)

Scrolling through code is like reading chess manuals without playing. You learn by breaking things:

• Our labs force you to debug synthesis warnings
• Optimize timing-critical paths
• Wrestle with clock domain crossings
  Designed by engineers who shipped 22nm chips – not academics.
  → Lab Preview: See the Raw Work

The Naked Truth About Outcomes

What You’ll Actually Build

1. RTL → Gates → Proven Silicon
   From behavioral Verilog to gate-level netlists validated against commercial PDK constraints.
2. Signal Integrity Fundamentals
   Learn why "it simulates" doesn’t mean "it works in silicon."
3. Portfolio-Ready Projects
   Demonstrate synthesis reports – not just waveforms.

Who Survives This Workshop?

• VLSI interns tired of coffee-fetching roles
• Software engineers done writing CRUD apps
• ECE grads who realize textbooks ignore DFM (Design for Manufacturing)

Curriculum: No Fluff, All Metal

Designed by Semiconductor Veterans (Not "Instructors")
Core Weaponry:

• Sky130 PDK Deep Dive: Libraries, DRC rules, stdcell characterization
• Synthesis-Aware Coding: Always-write-rules for flip-flops, state machines, memory
• Post-Synthesis Validation: Timing analysis, power estimation basics
• Project: Build a synthesizable CPU peripheral + full synthesis flow

Final Word: This Isn’t for "Learners." It’s for Builders.

If you want:
☑️ To list "RTL Design" on your resume without flinching
☑️ To understand why synthesis reports terrify new grads
☑️ To speak the language of foundries and physical design engineers

You’ve found your tribe.
Demystify Silicon. Start Building →