Hi
Only 48 hours left to join the SFAL-VSD Program and work on Project 1: RISC-V SoC Implementation using Synopsys EDA Tools and SCL180 PDK! This is your chance to gain hands-on experience with industry-standard workflows, from RTL
design to tapeout.
Project 1 Highlights
🔹 Design & Verify a RISC-V SoC:
- Synthesize and simulate using Synopsys Design Compiler and VCS.
- Resolve real-world challenges (e.g., blackboxed modules like housekeeping, RAM).
- Validate with Gate-Level Simulation (GLS) and analyze power (~72.7mW), area (~883k units), and timing reports.
🔹 SCL180 PDK Integration:
- Work with Semiconductor Laboratory’s 180nm process design kits, used for actual tapeouts.
- Learn to debug post-synth mismatches and prepare for physical implementation.
🔹 Open-Source & Reproducible:
- Clone a proven RISC-V SoC repository, mirroring industry practices.
Why SFAL-VSD?
✅
Synopsys Tool Mastery: Gain expertise in tools like Design Compiler, VCS, and ICC2 – the backbone of global ASIC design.
✅ Mentorship by Industry Leaders: Learn from Mr. Kunal Ghosh (VSD) and SFAL experts.
✅ Career-Ready Skills: Stand out with PDK-based design, RISC-V architecture, and verification experience.
Urgent! Registration Ends Soon
⏰
Deadline: 2 Days Left!
🔗 Secure Your Spot Now:
👉 https://www.vlsisystemdesign.com/sfal/
See What You’ll Achieve
- Functional Simulation vs. GLS: Validate your design with waveform comparisons (GTKWave).
- Synthesis Reports:
Optimize for power, area, and timing.
- Tapeout Readiness: Prepare for ICC2 flow and physical design.
Don’t Miss This Gateway to Semiconductor Careers!
The SFAL-VSD program bridges the gap between theory and industry practice. With Project 1, you’ll build a portfolio-ready RISC-V SoC while mastering tools used by top companies like Intel, AMD, and NVIDIA.
Act Now – Time is Ticking!
📆 Register Before the Deadline: https://www.vlsisystemdesign.com/sfal/
Best regards,
Team SFAL-VSD
Empowering Future ASIC/SoC Designers
P.S. “The SFAL-VSD program transformed my RTL skills into tapeout-ready expertise. Project 1’s Synopsys + SCL180 workflow was unparalleled!”
– Dhanvanti Bhavsar, Project Lead
This email is your final reminder. Registration closes in 2 days!
