Hi

What happens when VSD's next-gen technocrats like Dhanvanti and Ankit Mawle take the India Semiconductor Mission to heart? It sparks a vision for India called "One Tapeout Per Student (OTPs)" – a dream where every Indian engineering student experiences the journey from RTL to silicon.

An open-source RISC-V Reference SoC built on an India-based PDK was the missing piece in Indian VLSI education. It was a BIG decision for VSD to open-source its Reference RISC-V SoC design, but we knew it was necessary to bridge this gap. 

Here's the GitHub repo link for more details - 

https://github.com/vsdip/vsdRiscvScl180

Thanks to efabless and Caravel, which served as the base design, this vision took shape. It took over 7-8 months, with limited resources, to port the design to SCL180nm and complete functional and gate-level simulations - a challenging yet rewarding journey.

None of this would have been possible without the relentless support from the ecosystem:

• Montu Ji, Irfan, and Sankalp – for enabling access to Synopsys EDA tools for students across India through the ChipIN program.
• Deep Sehgal, Debjyoti Malik, and Uday Khambete from Semiconductor Laboratory (SCL) – for their unwavering support from day one.

While this marks an important milestone, the journey is far from over. There’s still Verification, Physical Design, SoC Implementation, Physical Verification, Tapeout, Tape-in, Packaging, PCB Design, and Testing left to bring this SoC into the hands of every Indian student.

If you believe in building India’s semiconductor future and want to contribute - drop an email. Together, we can turn One Tapeout Per Student (OTPs) into a reality.