Hi
After the roadshows, many of you asked how to build a basic RISC-V CPU from scratch. Well, here it is.
NASSCOM is backing VSD once again to bring you a comprehensive 10-day RISC-V program, designed to bridge the gap between learning and
real-world industry application. This isn’t just another online course—it’s a hands-on experience where you’ll design, implement, and build with a focus on practical RISC-V projects that will go straight to your resume.
https://www.vlsisystemdesign.com/riscv-based-myth/
What’s in it for you?
Along with mastering MYTH (Microprocessor for You in Thirty Hours), you get to work on a RISC-V design project that challenges your skills and sets you apart. Choose from:
- Branch Predictor Implementation: Build a simple two-bit predictor, a two-level predictor, or push boundaries with a TAGE predictor.
- Custom RISC-V Instruction: Extend the
ISA by designing and implementing a new instruction.
- GEMM/Convolution Optimization: Develop and test matrix multiplication or convolution in assembly, analyze performance, and compare pipelined vs. non-pipelined execution.
This is your chance to learn, build, and be part of the future of RISC-V.
Seats are limited - join now - https://www.vlsisystemdesign.com/riscv-based-myth/
See you inside.
