Hi

Here's the detailed week-wise content of VLSI Hardware design program

"Register Now" using below link. Last 2-days

https://www.vlsisystemdesign.com/hdp/

Week 1: Setting Up Environment and Introduction to RISC-V

• Objective: Get familiar with the environment, tools, and basic RISC-V workflow.
• Tasks:

1. Create a GitHub repository for storing all assignments and snapshots.
2. Install the RISC-V toolchain using the VDI shared on WhatsApp.
3. Follow the C-based Lab and RISC-V Lab videos. Replicate the steps on your machine.
4. Upload snapshots of:
   • Compiled C code.
   • RISC-V Objdump output.

• Deliverable: GitHub repo with snapshots and documentation.

Week 2: SPIKE Simulation and Optimization Levels

• Objective: Understand the impact of optimization flags in RISC-V.
• Tasks:

1. Perform SPIKE simulation with -O1 and -Ofast flags.
2. Upload the following to the GitHub repo:
   • Compiled C code.
   • RISC-V Objdump outputs for both flags.

• Deliverable: GitHub repo with simulation results and detailed observations.

Week 3: RISC-V Instruction Identification

• Objective: Decode and analyze RISC-V instructions.
• Tasks:

1. Identify instruction types (R, I, S, B, U, J) for given instructions.
2. Write the exact 32-bit instruction code for each in the specified format.
3. Upload all patterns to the GitHub repo.

• Deliverable: Documented 32-bit instruction patterns.

Week 4: Functional Simulation with Verilog

• Objective: Gain experience in Verilog functional simulation.
• Tasks:

1. Use the provided RISC-V core Verilog netlist and testbench.
2. Run functional simulation and capture waveforms.
3. Upload waveform snapshots and code to GitHub.

• Deliverable: GitHub repo with waveforms and simulation files.

Week 5: Building a 5-Stage Pipeline Processor

• Objective: Implement a pipelined RISC-V processor.
• Tasks:

1. Refer to detailed lab lectures on VSDIAT.
2. Build a 5-stage pipelined processor.
3. Append your initials to the clock signal name.
4. Upload simulation files and waveform snapshots.

• Deliverable: GitHub repo with design files, documentation, and waveforms.

Week 6: BabySoC Integration and Functional Verification

• Objective: Integrate rvmyth with BabySoC and verify outputs.
• Tasks:

1. Install required tools (Icarus Verilog, GTKWave, Yosys, OpenSTA).
2. Download BabySoC files and edit the top-level Verilog to integrate rvmyth.
3. Simulate and capture waveforms for PLL, DAC, and 10-bit outputs.
4. Ensure username and date are visible in the snapshots.

• Deliverable: GitHub repo with integrated design and waveform outputs.

Week 7: RISC-V Synthesis and Functional Comparison

• Objective: Perform synthesis and compare functional and synthesized outputs.
• Tasks:

1. Synthesize the RISC-V design.
2. Compare functional and synthesized waveforms for the first 20 cycles.
3. Capture and upload snapshots showing standard cells in GTKWave.

• Deliverable: GitHub repo with comparisons and synthesis snapshots.

Week 8: Timing Analysis and STA

• Objective: Perform Static Timing Analysis (STA) on RISC-V design.
• Tasks:

1. Set clock period, setup/hold uncertainties, and clock/data transitions.
2. Run STA using OpenSTA for all timing corners.
3. Upload snapshots of:
   • SDC file.
   • Setup and hold timing reports.
   • WNS/WHS table and graph.

• Deliverable: GitHub repo with detailed STA analysis and graphs.

Week 9: Advanced Physical Design Using OpenLane

• Objective: Understand advanced physical design workflows.
• Tasks:

1. Complete the "Advanced Physical Design using OpenLane" workshop.
2. Document all labs and workflows, including:
   1. Routed database.
   2. Quality of Results (QoR).
   3. Heatmap analysis.
   4. Upload detailed documentation to the GitHub repo.

• Deliverable: GitHub repo with detailed OpenLane design analysis and documentation.

Week 10: SoC Design Implementation Using OpenROAD

• Objective: Perform SoC design implementation using OpenROAD.
• Tasks:

1. Install OpenROAD flow scripts on your local machine.
2. Study and document:
   1. Basic OpenROAD flow setup.
   2. Macro flow setup.
   3. Include Routed Database, QoR analysis, and Heatmap visualization for BabySoC.
   4. Ensure detailed documentation is included in the GitHub repo.

• Deliverable: GitHub repo with SoC implementation project files and analysis.

Final Submission

• Ensure the GitHub repository is complete with:
  • Organized folders for each week's tasks.
  • Detailed README files for every task.
  • Clear documentation and snapshots.
  • All waveforms and comparison graphs.

Register Now using below link

https://www.vlsisystemdesign.com/hdp/