Hi
The SFAL-VSD SoC design and implementation program is more than just a learning experience; it’s an adventure into the heart of semiconductor design using Synopsys tools. Our current participants are pushing the boundaries of what’s possible, and we’re excited to share some of their groundbreaking work with you.
Real Experiments, Real Results
One of our current participants has conducted an experiment with two versions of
Phase-Locked Loops (PLLs), and the area results are nothing short of mind-blowing. While many have heard of PLLs, Digital-to-Analog Converters (DACs), and RISC-V cores, few have had the opportunity to see these elements in action, understand their sizes, and observe how their dimensions impact performance and accuracy metrics.
From Basics to Advanced
The upcoming SFAL-VSD SoC design and implementation program will take you on a journey from the basics to
advanced levels, and even beyond. You’ll engage in discussions and solve issues that the industry faces in real-time. This program isn’t just about learning; it’s about immersing yourself in the realities of semiconductor design.
Open Source IPs and RISC-V Cores
One of the highlights of our program is the use of open-source IPs and RISC-V cores. You can delve deep into the designs, right down to the MOSFET level, using Skywater 130nm technology. This
transparency allows you to fully understand and appreciate the intricacies of semiconductor design.
Enhance Your Resume
Participating in the SFAL-VSD program is not just about gaining knowledge; it’s about enhancing your resume and standing out in the competitive job market. The skills and experiences you gain here will raise the bar and get you noticed by top industry players.
Act Fast – Registration Closes Soon!
Don’t miss
this opportunity to elevate your career. Registration for the SFAL-VSD SoC design and implementation program closes in just 4 days. Secure your spot now and embark on a transformative journey into the world of semiconductor design.
A Glimpse into Our Work
Here are some visualizations from our current participant’s experiment with PLLs. These images showcase the differences in area and design between two versions of PLLs:
