It gives me such immense pleasure to announce another great example of outcome based industry-academia collaboration between VSD (VLSI System Design) and NIT Jamshedpur (NITJSR) which resulted into the development of ultimate PLL IP with loop filter issue resolved (Analog engineers can very well relate to complexities of building loop filters). Thanks to Prof. Kunal Singh and Prof. Chandradeep for leading this initiative from the front
 

This particular engagement and all other previous ones between VSD and Academia would not have been possible without the joint initiatives of eFabless, Skywater Technologies and Google. This model of industry-academia engagement is a win-win, not only for NIT-JSR, but for all colleges across India who are looking for cutting edge VLSI curriculum that's relevant to latest industry skills. It's a win-win for all academicians who would want to come in front and try out this model of engagement with industry and build great products/IPs for the world

 

It's a long journey, but it's a great start. Read this blog for mode details on IP specifications

 

All the best and happy learning