24hr Deal: Land Jobs in Semiconductors with Udemy

24hr Deal: Land Jobs in Semiconductors with Udemy - Lifetime Access @ Rs. 389!

Published: Wed, 11/29/23

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SoC planning and Physical Design

VSD - Physical Design Flow

VSD - Clock Tree Synthesis - Part 1

VSD - Clock Tree Synthesis - Part 2

VSD - SoC Design of the PicoRV32 RISCV micro-processor

VSD Intern – Mixed Signal Physical Design Flow

Sign-off analysis

VSD - Static Timing Analysis - I

VSD - Static Timing Analysis - II

VSD - Library characterization and modelling - Part 1

VSD - Static Timing Analysis (STA) Webinar

VSD - Signal Integrity

VSD - Timing ECO (engineering change order) webinar

VSD - Distributed timing analysis within 100 lines of code

RISC-V, Machine Intelligence in EDA/CAD

VSD - RISCV: Instruction Set Architecture (ISA) - Part 1a

VSD - RISCV: Instruction Set Architecture (ISA) - Part 1b

VSD - Making the Raven chip: How to design a RISC-V SoC

VSD – Mixed signal RISC-V based SoC on FPGA

VSD - Pipelining RISC-V with Transaction-Level Verilog

VSD - Machine Intelligence in EDA/CAD

Circuit design and layout fundamentals

VSD - Circuit Design & SPICE Simulations - Part 1

VSD - Circuit Design & SPICE Simulations - Part 2

VSD - Custom Layout

Analog IP design using SKY130

VSD Intern - OpenRAM configuration for 4kB SRAM using Sky130

VSD Intern – Analog Bandgap Reference design using Sky130

VSD Intern – Analog Comparator Design using Sky130

VSD Intern – DAC IP design using Sky130 PDKs – Part 1 (specifications design)

VSD Intern - DAC IP Design using Sky130 PDKs - Part 2 (circuit design)

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)

VSD Intern - 10-bit DAC design using eSim and Sky130

CAD/EDA automation and basic UNIX/IT

VSD - A complete guide to installing open-source EDA tools

VSD - A complete guide to installing Openlane and Sky130nm PDK

VSD - TCL programming - From novice to expert - Part 1

VSD - TCL programming - From novice to expert - Part 2

RTL design, Synthesis, FPGA and Verification

VSD - RTL Synthesis Q&A Webinar

VSD - Pipelining RISC-V with Transaction-Level Verilog

VSD – Mixed signal RISC-V based SoC on FPGA

VSD - Embedded-UVM(Open Source Verification and Emulation)

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