VSD interns are performing exceptionally well.

We are pleased to invite you to a free webinar where we will be discussing the innovative use of OpenFASoC and ALIGN tools for generating a complete core for a chip. This webinar aims to provide valuable insights into the process of designing analog blocks using Xschem, ALIGN, and Magic, as well as the significance of verilog files in linking various components of the OpenFASoC flow.

Webinar Details: 
Date: 18th May 
Time: 8pm IST 
Duration: 1-hr 
 

Agenda:

1. Introduction to OpenFASoC and ALIGN: Learn about these powerful tools and their role in generating a complete core for a chip.
2. Analog Block Generation with Xschem and ALIGN: Discover how Xschem is used to generate schematics and how ALIGN, along with Magic, aids in designing the layout for the analog block, specifically focusing on the creation of a self-toggling circuit called a ring oscillator.
3. 1-Bit ADC Analog Block Generation: Explore the process of using Xschem, ALIGN, and Magic to generate the schematic and layout for the 1-bit ADC analog block.
4. Verilog Files and OpenFASoC Flow: Understand the crucial role of verilog files in correctly linking the GDS and LEF files within the OpenFASoC flow. Learn about the top-level verilog file, "async_up_down.v," and the two macros, "COMPARATOR.v" and "RING_OSCILLATOR.v," which correspond to the cell names given in the GDS.
5. Flow Overview: Gain insights into the complete chip core generation flow, including steps such as Verilog cleaning and synthesis, APR, floorplanning, global placement, detailed placement, global routing, antenna check, and DRC check.

Our expert speaker will walk you through each step, providing practical tips and insights gained from real-world experiences. This webinar is ideal for chip designers, engineers, and enthusiasts who want to expand their knowledge of core generation using OpenFASoC and ALIGN tools.

To reserve your spot, please click on the following registration link: https://forms.gle/EuFYSFNnURykpfLg8

Don't miss out on this fantastic opportunity to enhance your chip design skills and learn about the latest advancements in core generation. We look forward to your active participation in the webinar.