Hi
After heavy requests, the cloud-based
RISC-V workshop with Steve Hoover is back from the 2nd to the 6th of November, and here's the registration link
A beginner-level 5-day workshop on “RISC-V based MYTH” (24hrs x 5 days on VSD-IAT platform)
When we say, “beginner level”, by end of the workshop you will understand
• RISC-V specs
• RISC-V software
• How to implement RISC-V basic specs using TL-Verilog
• Simulate your RISC-V core
*In short, you are going to write RTL and build the RISC-V core on your own*
Workshop Day-wise Content :
Day 1: Introduction to RISC-V ISA and GNU compiler
toolchain
- Introduction to RISC-V basic keywords
- Lab Work for RISC-V software toolchain
- Integer number representation
- Signed and unsigned arithmetic operations
Day 2: Introduction to ABI and basic verification flow
- Application Binary interface (ABI)
- Lab work using ABI function calls
- Basic verification flow using
iverilog
Day 3: Digital Logic with TL-Verilog and Makerchip
- Combinational logic in TL-Verilog using
Makerchip
- Sequential and pipelined logic
- Validity
- Hierarchy
Day 4: Basic
RISC-V CPU micro-architecture
- Microarchitecture and testbench for a simple RISC-V CPU
- Fetch, decode, and execute logic
- RISC-V control logic
Day 5: Complete Pipelined RISC-V CPU micro-architecture/store
- Pipelining the CPU
- Load and store instructions and memory
- Completing the RISC-V CPU
- Wrap-up and future
opportunities
All the best and happy learning
