Many of you were curious about the other VSD programs (both low cost and high cost)
and how they are different. So let me brief you about the upcoming 2 main programs (registration closes 4-days)
1) Hardware design Program ($999)
2) Udemy ($9-$10/course)
1) Hardware design Program ($999)
There is a hardware design program ($999) which is lab-intensive, mentor-based, 10 weeks, which can improve your chances of placement and jobs in design companies like Qualcomm, Nvidia, Google, and other top service companies
and also your chances of tape-out an IP with SKY130 https://www.vlsisystemdesign.com/hdp/
Popular projects are the below:
Physical Design and Static Timing Analysis |
rvmyth integration with PLL, DAC and SRAM using
Sky130 | RISC-V based SoC design, implementation and tapeout using VSD Sky130 IPs |
Performance characterization
for VSDBabySoC comprising of RISC-V core, PLL and DAC | Analyze and characterize RISC-V based VSDBabySoC for all timing corners, fix timing violations, ECO, implement and
tapeout |
New- Enabling SDC switches in Yosys | Yosys is an open-source logic synthesis tool. Unfortunately, there is no support for the regular SDC in Yosys. The aim of the project is to take certain specific constraints in SDC
like set_max_delay , set_input_delay ,
set_input_transition , etc and enable the equivalent features in Yosys by creating custom synthesis scripts. The scope of this project gives very good exposure to
Verilog coding skills, Working on synthesizer, Logic optimization knobs in logic synthesis, Design constraints |
2) Udemy ($9 to $10/course)
Udemy (less paid) is theory+labs, which you need to do with self-learning. The order in which you need to take the courses is given below along with their discounted links