Hi

 

Did you know the best part of learning computer architecture? You can build a basic CPU using muxes, which you have learnt as a part of digital logic design. On top of that, TL-Verilog makes it simple to pipeline your CPU and convert your final outcome into standard IEEE format verilog netlist in few seconds which is FPGA proven and Silicon ready

 

Thanks to OSFPGA, for the first time, you are receiving a $70 workshop at just $30, which is more than 55% discounted than the original price. Its limited to top 100 participants and registration closes in 24hrs

 

Here's the link for registration

https://pages.razorpay.com/osfpga-riscv

 

All the best and happy learning