Mission OSFPGA 3-8-10

Published: Fri, 05/20/22

Does this sound like an Army mission with a secret code number? No, it's not. So what is "Mission OSFPGA 3-8-10"?

It is a creative way to remind all of you that you have the last 3-days to register for the high-intensity lab-based RISC-V workshop, last 8-days to register for the Mixed-signal FPGA workshop and last 10-days to register for the FPGA design workshop at Limited Time OSFPGA Sponsored Price

The below link has details of each Chapter covered in the workshop

https://osfpga.org/osfpga-training/

See details below. So low cost education is a mission for us. And hence "Mission OSFPGA 3-8-10"

All the best and happy learning

Course name 25th-29th May	RISC-V based MYTH (Microprocessors for you in thirty hours)
Course name 25th-29th May
Chapter 1	Introduction to RISC-V ISA and GNU compiler tool-chain
	1. Introduction to RISC-V basic keywords
	2. Labwork for RISC-V software tool-chain
	3. Integer number representation
	4. Signed and unsigned arithmetic operations

Chapter 2	Introduction to ABI and basic verification flow
	1. Application Binary interface (ABI)
	2. Lab work using ABI function calls
	3. Basic verification flow using iverilog

Chapter 3	Digital Logic with TL-Verilog and Makerchip
	1. Combinational logic in TL-Verilog using Makerchip
	2. Sequential and pipe-lined logic
	3. Validity
	4. Hierarchy

Chapter 4	Basic RISC-V CPU micro-architecture
	1. Micro-architecture and testbench for a simple RISC-V CPU
	2. Fetch, decode, and execute logic
	3. RISC-V control logic

Chapter 5	Complete Pipe-lined RISC-V CPU micro-architecture/store
	1. Pipe-lining the CPU
	2. Load and store instructions and memory
	3. Completing the RISC-V CPU
	4. Wrap-up and future opportunities

Course name 30th May	Mixed-signal RISC-V based SoC on FPGA
Course name 30th May	Mixed-signal RISC-V based SoC on FPGA
Chapter 6	Mixed-signal RISC-V based SoC on FPGA
	1. Introduction to FPGA IPs
	2. Mixed-signal SoC details with RISC-V core and PLL IP
	3. Mixed-signal FPGA flow

Course name 1st-5th June	FPGA - Fabric, Design and Architecture
Course name 1st-5th June	FPGA - Fabric, Design and Architecture
Chapter 7	FPGA introduction
	1. What Is FPGA And FPGA Architecture?
	2. Vivado-counter on Basys board
	3. VIO Counter on Basys board

Chapter 8	OpenFPGA
	1. Introduction
	2. VPR flow
	3. VTR flow
	4. Earch and Basys3 comparison

Chapter 9	Introduction to RISC-V core programming on Vivado
	1. RVMyth vivado rtl-to-synthesis
	2. RVMyth Vivado synthesis-to-bitstream

Chapter 10	Introduction to SOFA FPGA Fabric IP
	1. SOFA counter area
	2. SOFA counter timing
	3. SOFA counter post impl
	4. SOFA counter power

Chapter 11	RISC-V core on custom SOFA fabric
	1. SOFA-RVMyth run
	2. SOFA-RVMyth timing and area
	3. RVMyth-post impl netlist
	4. SOFA-RVMyth Vivado simulation

Thanks & Regards

Kunal P Ghosh

"A pessimist always sees difficulty in every opportunity, An optimist always sees opportunity in every difficulty"