Analog

10 bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

{Project code : DAC}

The project aims to design a 10-bit Potentiometric Digital to Analog Converter using end-to-end Open-source EDA tools. The target is to design a 10-bit potentiometric DAC with 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference using a sky130nm technology node.

High-Frequency analog VCO design and implementation using Sky130

{Project code : KCEDVCO}

200MHz, 400MHz and 915MHz VCO design using Sky130nm - from specification to tape outflow

Low Dropout Regulation: A low-dropout regulator (LDO) is a DC linear voltage regulator that can regulate the output 
the voltage that is powered from a higher voltage input. 

{Project Code: LDO}

LDO  Specifications:
1.     Technology: Google Sky water 130nm 
2.     Input power supply range: 2-to-5 V
3.     Output Voltage: 1.8 V
4.     Load current: 10 mA
5.     Temp range: -40 to 125 Degree cent.
6.     Circuit current: 0.5 mA
7.     Reference Voltage: 1.2 V @ < 50 ppm

NEW - Circuit Design for Capacitive Sensing - Touch/Pressure

{Project code -  CDCST}

The capacitance to digital converter (CDC) are being extensively used in Biomedical diagnostics, Water and level sensing applications in the Industrial sector, MEMS sensor interface and plenty of hobby projects by young engineers. The basics of capacitance sensors, types of cap sensors - Floating and Grounded and their construction are discussed. Learn about the interdigitated Capacitor platform for many Gas Sensing applications and pressure sensing applications. 

Physical Design and Static Timing Analysis 

rvmyth integration with PLL, DAC and SRAM using Sky130

{Project code - RPDS}

RISC-V based SoC design, implementation and tapeout using VSD Sky130 IPs

Performance characterization for VSDBabySoC comprising of RISC-V core, PLL and DAC

{Project code - PCVRPD}

Analyze and characterize RISC-V based VSDBabySoC for all timing corners, fix timing violations, ECO, implement and tapeout

rvmyth: RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for SKY130   

{Project Code: ROLS}

Take the LibreSilicon Standard Cells for the SKY130 process (https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.html) and synthesise an RVMYTH design using those standard cells with OpenLane, preferably directly into an EFabless Caravel User-Space.

Parallel Static Timing Analysis

{Project Code: PSTA}

In this project, we will build a parallel STA algorithm on top of the open-source software, OpenTimer. We will start with understanding the runtime bottleneck of OpenTimer on a large industrial design of millions of gates. Then, we will dive into the core algorithm of OpenTimer and learn how to parallelize it using manycore CPU parallelism. Finally, we will demonstrate the speed-up compared to the original version.

New- Enabling SDC switches in Yosys

{Project Code: ESSY}

Yosys is an open-source logic synthesis tool. Unfortunately, there is no support for the regular SDC in Yosys. The project aims to take certain specific constraints in SDC
like set_max_delay, set_input_delay, set_input_transition, etc and enable the equivalent features in Yosys by creating custom synthesis scripts. The scope of this project gives very good exposure to
Verilog coding skills, Working on synthesizer, Logic optimization knobs in logic synthesis, Design constraints