Day1:
- Introduction to FPGA
- Counter example using Vivado
- Counter Verilog explanation and implementation using Vivado
- Vivado timing, power, and area measurement for counter
- Introduction to VIO
Day2:
- Introduction to OpenFPGA and VTR (verilog-to-routing)
- Introduction to VPR (versatile-place-and-route) using basic Earch fabric
- Counter example using VPR/VTR openfpga flow
Day3:
- Introduction to basic RISC-V core – rvmyth
- Rvmyth – Vivado RTL to synthesis flow
- Rvmyth – Vivado Synthesis to bitstream
Day4:
- Introduction to opensource SOFA FPGA fabric
- Steps to run counter example on SOFA
- Characterize counter example in terms of area and timing
- Post-implementation netlist and simulation using SOFA
Day5:
- Steps to run RISC-V Core - on SOFA
- Characterize RVmyth in terms of performance and area
- Steps to generate rvmyth post-implementation netlist
- Confirm RVmyth on SOFA behavioral simulation using Vivado
All the best and happy learning
