Hi

 

There is a huge difference between what people think about STA and what STA really is. There is a huge gap in how Physical Designers (including myself) look at STA and how STA engineers look at it. There are many STA performance metrics which Physical designers miss out on, and missed one's are sometimes a major factor for chip failure.

 

I have experienced this first-hand. Irrespective of what your profile is (student, Physical designer, DFT engineer, RTL designer, Professor), if you wish to be in semiconductor for a long run, you need to look at your chip beyond setup/hold violations, because STA sign-off analysis is way beyond standard setup/hold violations.

So here's an exclusive STA cloud lab based workshop using OpenSTA and Sky130 PDKs.

Registration link (Last 24hrs to register) and workshop content-

https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/

All the best and happy learning